Densitometer

ABSTRACT

A vibration densitometer including a closed loop electromechanical oscillator for vibrating a fluid immersible vane. A digital output directly proportional to density is achieved through a unique digital squarer. The densitometer is an all digital system. In the loop, a tracking filter is provided. Separate search and track automatic gain control feedbacks are provided. A threshold detector controls clamps and a gate to cause the voltage controlled oscillator of a first phase lock loop to search or track the vane resonant frequency. The threshold detector also effects the search feedback. A phase adjustment circuit and a second phase lock loop are employed to impress a sine wave voltage component on the vane driver of a phase which creates maximum efficiency.

United States Patent Schlatter Apr. 15, 1975 DENSITOMETER 3.772.91511/1973 Stamler 235/151.34 x 3.775.597 ll I973 N b 235 lSl.3 X

[75] Inventor: Gerald Lance Schlatter, Boulder. Ovem er Colo PrimaryExaminer-Eugene G. Bot: [73] Assignee: International Telephone andAssistant Exam1'ner-Edward J. Wise Telegraph Corporation. New YorkAlrorney. Agent. or Firm-A. Donald Stolzy 221 Filed: Dec. 10, 1973 [57]ABSTRACT Appl. No.: 423,409

A vibration densitometer including a closed loop electromechanicaloscillator for vibrating a fluid immers ible vane. A digital outputdirectly proportional to density is achieved through a unique digitalsquarcr.

[52} US. Cl. 235/l51.3; 73/32; 235/l5l.34;

235/1505?J The densitometer is an all digital system. in the loop. [5 1]Int Cl G06 15/34; Gm 9/00 a tracking filter is provided. Separate searchand track [58] Fwd 0' Search 235/1513 [5134 92 MT automatic gain controlfeedbacks are provided. A 235/92 CP 92 R 197 73/30 threshold detectorcontrols clamps and a gate to cause v [94 M the voltage controlledoscillator of a first phase lock loop to search or track the vaneresonant frequency. [56] References Cited The threshold detector alsoeffects the search feedback. A phase adjustment circuit and a secondphase UNITED STATES PATENTS lock loop are employed to impress a sinewave voltage h 33 3; :2 component on the vane driver of a phase whichcrelfetfl... 3,769,500 10/1973 Schlatter 235 15134 x mmmum emclency'3,769,831 1 [H973 Schlatter 73/32 41 Claims, 22 Drawing FiguresTENTEHPR. 5am

SHEET 5 BF 9 FIGJI.

FIG. I2.

[)ENSITOMETER BACKGROL'ND OF THE INVENTION This invention relates tovibration densitometers. and more particularly. to an improveddensitometer and a digital function generator therefor for producing adigital output directly proportional to density.

\'ibration densitometers are essential digitally inclined instrumentsbecause the density they indicate is a function of their ibrationalfrequency. Howe\ er. thc present time. no highly accurate or inaccuratedigital linearization circuit has been employed with such in struments.

SUMMARY OF THE INVENTION In accordance with the present invention. theabovedescribed and other disadvantages of the prior art are overcome byproviding a digital function generator for very accurately lincarizingthe output of the electromechanical oscillator of a vibrationdensitomcter.

Other features of the invention reside in the use of a search or sweepfeedback and an automatic gain control (AGC) feedback.

Still another feature of the invention resides in the use of a thresholddetector for search. track and feed back control.

A further feature of the invention resides in the use of a phaseadjustment circuit and phase lock loop to ef fect ma\imum driveefficiency.

The above-described and other advantages of the present invention willbe better understood from the following detailed description whenconsidered in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings. which are to beregarded as merely illustrati\e:

FIG. I is a block diagram of a densitomcter constructed in accordancewith the present invention;

FIG. 2 is a block diagram of a loop circuit shown in FIG. I;

FIG. 3 is a schematic diagram of an input circuit. an AGC amplifier. atracking filter. two zero crossing detectors. two phase detectors. twolow pass filters and a clamp shown in FIG. 2;

FIG. 4 is a block diagram of a phase lock loop shown in FIG. 2;

FIG. 5 is a schematic diagram of a phase adjustment circuit. an AND gateand an inverter shown in FIG. 2;

FIG. 6 is a block diagram of another phase lock loop shown in FIG. 2;

FIG. 7 is a schematic diagram of a low pass filter shown in FIG. 6:

FIG. 8 is a schematic diagram of a driver amplifier shown in FIG. 2;

FIGS. 9. III. II. I2 and 13 are graphs of a group of waveformscharacteristic of the operation of the loop circuit shown in FIGS. 1-8.inclusive:

FIG. I4 is a more detailed block diagram of the digital functiongenerator shown in FIG. 11;

FIG. is a more detailed block diagram of a square low digital computershown in FIG. 14;

FIG. I6 is a still more detailed block diagram of a divider and ratemultiplier shown in FIG. 15;

FIG. 17 is a front elevational view of a set of lamps conventionallyused to. when gated on at appropriate (ill intervals. display selecthelyone of the ten digits l-9 and (I:

FIG. I8 is a block diagram of alternative embodiments of a divider andrate multiplier shown in FIG. 15:

FIG. I) is a switch matrix which may be employed with a counter shown inFIG. 18 to produce serial pulses in serial groups where the number ofpulses in a group is directly proportional to the binary setting of theswitches in the matrix of FIG. I9;

FIG. 20 is a block diagram of an alternative embodiment ofthe digitalfunction generator shown in FIG. I;

FIG. 2I is a block diagram of a conventional off-set digital computer;and

FIG. 22 is a graph ol'a group of waveforms characteristic of theoperation of the digital function generator shown in FIG. 20.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the drawings. in FIG. I. avibration densitomcter probe is indicated at 34' having a driver coil 23a \ane 24. a piezoelectric crystal 25 and a preamplifier 26.

Probe 34' has an input lead 27 and an output lead 28.

Other blocks shown in FIG. I are a loop circuit 1 a digital functiongenerator and utilization means SI. Loop circuit 29 has an input lead 32and output leads 33 and 34. Digital function generator 30 has an inputlead connected from loop circuit output lead 34. The output of digitalfunction generator 30 is connected to utilization means 31.

The output lead 28 of probe 34' is connected to the input lead 32 ofloop circuit 29. The input lead 27 of probe 34' is connected from theoutput lead 33 of loop circuit 29. Probe 34' and loop circuit 2) form aclosed loop electromechanical oscillator. \ane 24 is submerged in afluid. The density of the fluid is a function of the frequency at whichvane 24 \ibrates.

Digital function generator 30 may have its input lead 35 connected fromlead 33 or at other points in loop circuit 2). Loop circuit 29 impressesa square wave voltage on input lead 35 of digital function generator 30having a mark-to-space ratio of I11.

Utilization means 3] shown in FIG. I may be a density indicator. aspecific gravity indicator. a process controller or otherwise.

Throughout this description. reference will be made to the textofcertain L'.S. patents and LS patent applications. These patents andpatent applications are listed for convenience forthwith.

Reference is hereby made to the following patents:

l. LS. Pat. No. 3.677.067.

Z. L'.S. Pat. No. 3.706.220.

3. L15. Pat. No. 3.738155.

4. US. Pat. No. 3.74I.tltlll.

The foregoing patents of paragraphs l l. (1].(3) and (-l) arehereinafter referred to as patents PI. P2. P3 and P4. respectively.

Reference is hereby made to the following L'S. patent applications:

I. LYS. Pat. application Ser. No. 161.025 filed July 9.

I97l. for DENSITOMETER COMPONENTS by G. L. Schlatter.

2. ES. Pat. application Ser. No. INS-l8 filed Oct. l2. l97l. for FLLIDSENSING SYSTEMS by G. L. SchIatter-C E. Miller.

3. US Pat. application Ser. No. 270.335 filed July It). I972. forDENSITOMETER by G. L. Schlatter.

4. I15. Pat. application Ser. No 2S9.77U filed Sept.

l6. I973. for \IBRATION DENSITOMETER AP- PARATLS h G. I.. Schlatter.L'.S. Put. application Ser. \o. 299.638 filed Oct. Ill. I972. for METHODOF AND APPARATL'S FOR RESOLYING A COMPLEX A.C. \'OI..T- AGE OR CLRRENTINTO ITS VECTOR ('O.\I- PONENTS h N. A. .\larshall.

6. L5. Pat. application Ser. No. 3()9.I6tfiled .\'o\. 24. I972. forDENSITOMETER AND PROBF. THEREFOR h C. E. Miller 7. [5. Pat. applicationSer. No. FII LZFU filed Nov 24. 1972. for FLL'ID SENSING SYSTEMS h G. L.Sehlatter-C. E. Miller.

6. LS. Pat. application Ser. No. 318.836 filed Dec.

27. I972. for FLL'ID DENSITY DIGITAL COM- PI'TER h M. H. Nmemher.

9. CS. Pat. application SCI. No. 321.662 filed Jan. 6.

19173. for PILSE TRAIN MODIFICATION CIR- CI'IT h) P. 7. KalotayG. A.Fitzpatrick.

II) US. Pat. application Ser. No. 332.74l filed Fch I5. I97]. for METHODOF MAKING A VIBRA- TIO,\ DENSI'I'OMETER h C. Ii. Miller.

The foregoing LIS. patent applications listed in para graphs t l l-lIll). inclusiie. are referred to hereinafter as applications Al-AIU.respectivel v Prohe 34' shown in FIG. I ma} he comentional. Alternatnelprobe 34 ma he similar to or identical to a prohe shown in an of thepatents PI P4. Prohe 34' ma} also he similar to or identical to theprohe shown in applications A2. A6. A7 or Alt).

Preamplifier 26 shown in FIG, I mav he conven tional. Preamplifier 26ma) also he similar to or identical to either one of the preamplifiersshown in application A4 or A5.

Loop circuit 29 is shown in FIG. 2 including an input circuit 36. an AGCamplifier 37. a tracking filter 38.;1 zero crossing detector 39. aone-shot multiviln'ator 40. an in\erter 41. a clamp 42. a phase lockloop 43. a squarer 44. an AND gate. an inierter 46. a phase lock loop 47and a drive amplifier 48 connected in succession as serial stages frominput lead 32 of input circuit 29 to its output lead 33 and connectedrespectnel from the output lead 28 of probe 34' to the input lead 27 ofprobe 34.

In FIG. 2. other stages are a zero crossing detector 49. a phasedetector 50. a low pass filter 51. a phase de tector 52. a low passfilter 53. a threshold detector 54. an inierter 55. a clamp 56. a sweeposcillator 57. an emitter-follower 58. a sawdooth generator 59 and aphase adjustment circuit 60.

AGC amplifier 37 has an AGC input lead 6] connected from the output ofclamp 56.

Tracking filter 38 has two output leads 62 and 63. Tracking filteroutput lead 63 is connected to the input of mm crossing detector 49. Theoutput of Zero crossing detector 49 is connected to one input 64 ofphase detector 50. A junction is provided at 65 from which an outputlead 66 of AGC amplifier 37 is connected. Tracking filter 38 has twoinput leads 67 and 68. Tracking filter input lead 67 is connected frontjunction 65.

Phase detector 50 has a second input lead 69 connected from junction 65.The output of phase detector 50 is connected to the input of low passfilter 51. The output of low pass filter l is connected to the inputlead 68 of tracking filter 38.

The purpose of Veto crossing detector 59. phase de tector 50 and lowpass filter 51 is to cause tracking filter 38 to track the frequenc ofoutput signal of AGC amplifier 37. The signal on the tracking filter 68.thus. causes the passhand thereof to straddle the frequenc of the inputto tracking filter 38 over input lead 67.

The output of tracking filter 38 on output lead 62 thereof is 90 out ofphase with the signal on the output lead 63 thereof. The signal from thetracking filter output lead 62 is impressed upon zero crossing detector39 and phase detector 52. The output of zero crossing detector 39 isimpressed hoth upon phase detector 52 and one-shot 40. The output ofphase detector 52 is impressed upon low pass filter 53.

A junction is ro\ided at 70 connected from the output of low pass filter53. A lead 71 is connected from junction 70 to input circuit 36 to theAGC input of an amplifier therin for automatic gain control.

Threshold detector 54 has an input 72 connected from junction 70. Inputlead 72 of threshold detector 54. when below a predetermined potential.causes the potential of the output lead 73 of threshold detector 54 togo either high or low. The output lead 73 of threshold detector 54 is.thus. for example. either ground or +15 \olts or +\'l. as definedhereinafter. When the output of low pass filter 53 is below thepredetermined potential. output lead 73 of threshold detector 54 is atground.

Threshold detector 54 operates both of the clamps 42 and 56 and thesweep oscillator 57. Clamp 56 and sweep oscillator 57 are operatedthrough the inverter Imerter 55 has an output lead 74 which also assumespotentials of \'l or ground.

Clamp 42 either passes the output of inverter 4I to the phase lock loop43 or in the other state of the threshold detector 54. clamp 42 ha\ ingan output lead 75. is operated to clamp the output lead 75 to ground.The output of imerter 55 is simply the reverse of the output detector54. When the output of inverter 55 is high. sweep oscillator 57 receivespower. When the output of in\ erter 55 is low, the output of sweeposcillator 57 is at ground.

Emitter follower 58 is connected between sweep os cillator 57 and phaselock loop 43. Phase lock loop 43 has an output lead 76 which isconnected to squarer 44. Junctions are provided at 77 and 78. Squarer 44has an output lead 79 connected to junction 78. Junction 78 is connectedto junction 77. Clamp 56 is connected from junction 77 to AGC amplifierinput lead 6].

When the output of threshold detector 54 is high. loop circuit 29 istracking and opens clamp 42 to unground the output lead 75 thereof.Conversely. at the same time. inverter 55 grounds the input to sweeposcillator 57 and disables it. During tracking. inverte 55 also disablesthe output of clamp 56 by a connection 80 from inverter output lead 74to clamp 56.

During searching. threshold detector 54 holds the output of clamp 42 atground while inverter 55 operates sweep oscillator 57 and clamp 56passes the output of squarer 44 to the AGC input lead 61 of AGCamplifier 37.

In FIG. 2.junction 77 is connected to digital function generator 30shown in FIG. 1.

AND gate 45 receives an input from junction 78 and from an output lead81 of phase adjustment circuit 60.

Saw-tooth generator 59 has an input lead 82 connectd from junction 78.and an output lead 83 connected to an input of phase adjustment circuit60.

Circuit 60 is manually adjustable to manually adjust the sine wavecomponent of the output \oltage of driver amplifier 48 through the useofcertain structures including the phase adjustment circuit 60. itself.and phase lock loop 47. This adjustment makes the electromechanicaloscillator oscillate with ma\imum effi ciency.

OPERATION In the embodiment of the invention shown in FIG. 1. probe 34'and loop circuit 29 provide an electromechanical oscillator whichoscillates at a frequency dependent upon the density of the fluid inwhich vane 24 is immersed. The same is true of the pulse repetitionfrequency of the square wave voltage applied to the input lead 35 ofdigital function generator 30.

Digital function generator 30 may be described as a digitallinearization circuit. It produces a digital output directlyproportional to density from the input signal thereto impressed upon theinput lead thereto.

In FIG. 3. input circuit 36 is shown for connection from preamplifier 26in FIG. I. Input circuit 36 has input leads 84 and 85. Input circuit 36has various junctions 86. 87. 88. 89 and 90. A capacitor 91 is connectedfrom input lead 84 to junction 86. Input lead is connected to junction87. A resistor 92 is connected between junctions 86 and 87. Atransformer 93 is prov ided with a primary winding 94 and a secondarywinding 95. Primary winding 94 is connected between junctions 86 and 87.Secondary winding 95 has leads 96 and 97. lead 97 being grounded. Apotentiometer 98 is proided having a winding )9 and a wiper I00. Winding99 is connected from transformer secondary lead 96 to ground. Wiper 100is connected to junction 88. A diode 101 is connected from junction 88to ground and poled to be conductive in a direction toward ground. Adiode 102 is connected from junction 89 to ground and poled in adirection to be conductive toward junction 89. Junctions 88 and 89 areconnected together.

A capacitor 103 is connected from junction 89 to the non-inverting inputof a differential amplifier 104. Junction 90 is connected from theinverting input of amplifier 104. A capacitor 105 is connected fromjunction 90 to ground. A resistor 106 is connected from junction 70 tojunction 90.

All of the blocks shown in FIG. 2 may be entirely conventional exceptphase lock loop 43 and phase adjustment circuit 60.

In FIG. 3. a calibration frequency may be provided over input lead 107.if desired. and impressed upon junction 65 through a circuit 108.Circuit 108 includes junctions I09 and 110. A resistor III and acapacitor 112 are connected in series in that order from lead 107tojunction 109. A diode 113 is connected from ground to junction I09.and is poled to be conductive in a di rection toward junction 10). Adiode 114 is connected from junction to ground and is poled to beconductive in a direction toward ground. Junctions 109 and 110 areconnected together. Junctions I10 and 65 are also connected together.

AGC amplifier 37 has junctions I15. I16. I17 and 118. A capacitor 119 isconnected from an output lead 120 of amplifier 104 in input circuit 36tojunction 115. A resistor 121 is connected from junction 115 to I25.Diodes 123 and 124 are connected in succession in that order from lead80 to lead 61.

A junction is shown at 126. The anodes ofdiodes I23 and 124 areconnected to junction 126. The cathode of diode I23 is connected to lead80. l'he cathode of diode 124 is connected to lead 61.

Junction 77 is connected from junction 78. as described previously.

In FIG. 3. in AGC amplifier 37.11 resistor 12) is connected from lead 61to junction I16. Junctions 116 and 118 are connected together. Aresistor I28 is con nected from junction 118 to ground. A resistor 12)is connected between junctions I17 and 118. Amplifier 122 has an outputlead connected to junction I17. A capacitor 131 and a resistor 132 areconnected in series in that order from junction 117 to junction 65.

Again. in FIG. 3. junctions are provided at 133. I34. I35. I36 and 137.Junction 133 is connected from lead 67. A resistor 138 is connected fromjunction 133 to ground. A resistor 13) is connected between junctionsI33 and 134. A capacitor 140 is connected between junctions I34 and 136.A resistor 14] is connected between junctions 135 and 136. Adifferential amplifier 142 is provided having an inverting inputconnected from junction 136. a grounded non-inverting input. and anoutput lead 143 connected to junction I35.

Tracking filter 38 is connected to Zero crossing de tector 39 and phasedetector 52 via a lead I44 con nected from junction 135 in trackingfilter 38 to a junction 145. Zero crossing detector 39 and phasedetector 52 are connected from junction 145. In FIG. 3. track ing filter38 has a field effect transistor 146 including a source I47. a drain I48and a gate 149. Source I47 is grounded. A resistor 150 is connected fromdrain 148 to junction I37. Junctions I34 and 137 are connected together.A resistor 151 is connected from junction 137 to ground. A resistor I52is connected from gate 149 to lead 68.

Zero crossing detector 49 has junctions at 153 and 154. A capacitor I55is connected from junction 137 to junction 153. A third junction 156 isalso provided and maintained at potential +\'2. A resistor 157 isconnected between junctions I53 and 156. A resistor 158 is connectedfrom junction 156 to the non-inverting input lead of a differentialamplifier I59. Junction 153 is connected to the inverting input lead ofamplifier I59. Amplifier 159 has an output lead 160 connected tojunction 154. A resistor 16] is connected from junction 154 to potential+\'2.

Lead 64 connects junction 154 to the input of a conventional amplifier162 in phase detector 50. Phase de' tector 50 also includes aconventional electronic or transistor switch 163 which is connected fromand o erated by amplifier I62. Switch I63 is connected by a lead 69 fromjunction 65 to low pass filter 51 at junc tion 164 therein. Low passfilter 51 has various other junctions 165. I66. I67 and 168. A resistor16') is connected from junction 164 to ground. A resistor 170 isconnected between junctions 164 and 165. A capacitor 171 is connectedfrom junction to ground. A resistor 172 is connected between junctionsI65 and 167. Junctions I66 and 167 are connected together. Apotentiometer is provided at 173 having a winding I74 and a wiper 175.Winding 17-1 is connected between +\I and I. A resistor I76 is connectedfrom wiper I75 to junction I66. A differential amplifier I7I is pro-\ided having an output lead 178 connected to junction I68. A capacitor179 is connected hetween junctions I66 and I68. Junction I67 isconnected to the imerting input lead of amplifier I77. 'lhe nonin\erting input lead of amplifier I77 is connected to ground. Lead 68and resistor I52 are connected in series in that order front junctionI68 to gate I49 of field effect transistor I46.

Zero crossing detector 39 includes four junctions I80. I8I. I82 and I83.A capacitor I84 is connected from junction I45 to junction I80. Aresistor I85 is connected between junctions I80 and H ll. An amplilieris provided at I86. A resistor I87 is connected from junction 181 to thenon-inverting input of amplifier I86. Junction 180 is connected to theimerting input of amplifier I86. Amplifier I86 has an output lead I88connected to junction I83. Junctions I8I and I82 are connected together.A resistor I89 is connected from junction I82 to potential +\'I. Aresistor I9" is connected from junction I83 to potential +\'2. A letterdiode I9I is connected from junction I82 to ground and is polcd to hehack biased between potential +\'I.

Phase detector 52 may he identical to phase detector 50 and. therefore.will not he described except that phase detector 52 has an input leadI92 connected from junction I45 to a switch 193 \ia a resistor I94.Switch I93 is connected to lo\\ pass filter 5. to a junction I95 ia adiode I96 poled to he conductive toward junction I95. Low pass filter 53also has junctions I97. Wis and 199. A resistor 200 is connected fromjunction 195 to ground. A capacitor 20] is connected from junction I97to ground. Junctions I95 and 197 are connected together: A differentialamplifier 201 has an output lead 203 connected to junction I98. JunctionI97 is connected to the non-inverting input of amplifier 202. l'heimerting input of amplifier 202 is connected from junction I99.Junctions I98 and 70 are connected together. A resistor 204 is connectedbetween junc tions I98 and I99. A resistor 205' is connected fromjunction I99 to ground.

In FIG. 4. sweep oscillator 57 is again shown with emitterfollower 58and phase lock loop 43. Emitterfollower 58 includes a transistor 205 ha\ing an emitter 206 connected from the output of sweep oscillator 57. acollector 207 and a base 208. Collector 207 is connected to potential\'I. Emitter-follower 58 has a junc tion 209 connected from emitter 206.A resistor 210 is connected from junction 209 to ground.

Junction 209 is connected to a junction 21] in phase lock loop 43. Phaselock loop 43 includes a phase detector 2I2. a low pass filter 213. aresistor 214. a resistor 2I5 and a \oltage controlled oscillator YCO)2I6.

VCO 2I6 ma) or may not produce a sawdooth output \oltage and may or maynot he comentiomtl in each case. If the output \oltage of \'C() 16 is asaw tooth. squarer 44 and saw-tooth generator 59 in FIG. 2 may heomitted and lead 76 connected directly to junction 78 and connecteddirectly to the input of phase adjustment circuit 60.

Phase lock loop 43 has an input lead 2l7 connected front clamp outputlead 75 shown in FIG. 2. and the output lead 76 connected to the inputof squarer 44.

Phase detector 212 has an input connected from lead 217 and a secondinput connected from the output of \'C() 216 which is also connected tolead 76. During tracking. the output of phase detector 212 is impressedupon the input of \(O 2I6 via a low pass filter 2I3. resistor 214 andresistor 215 in succession in that order. resistor 214 being connectedfrom the output of low pass filter 213 to junction 2II. Resistor 2l5 isconnected from junction 2]] to the input of \'CO 2I6.

During tracking. transistor 205 of emitter-follower 58 is cut off andthe output of sweep oscillator 57 is grounded because of the groundedoutput of imerter During searching. lead 2I7 is grounded in clamp 42.The output of low pass filter 2| is then grounded. 'Irunsistor 205 is nolonger cut off and the output of sweep oscillator 57 passes to VCO 2I6\ia emitterfollower 58.

In FIG. 5. phase adjustment circuit 60 is shown connected from saw-toothgenerator 59 o\er lead 83. Phase adjustment circuit 60 has two junctions2ll-l and 219. A capacitor 220 is connected from lead 83 to junction218. A resistor 22] is connected from junction 218 to ground. A resistor222 is connected between junctions 2I8 and 219. Junction 219 ismaintained at potential +\'I. A potentiometer 223 is shown liming awinding 224 and a wiper 225. Winding 224 is connected hetween junction2I9 and ground. Wiper 225 is connected to the imcrting input ofdifferential amplifier 226. The nominverting input of amplifier 226 isconnected from junction 213.

In FIG. 5. AND gate 45 has junctions 227 and 228. A resistor 229 isconnected from potential to junction 228. In phase adjustment circuit60. amplifier 226 has an output lead 230 connected to junction 228.

In AND gate 45. a resitor 231 is connected from junction 227 topotential +\'I. A resistor 232 is connected from junction 227 to ground.AND gate 45 has a differential amplifier 233 with an output lead 234connected to junction 228. Amplifier 233 has an inxerting inputconnected from junction 227. and a noninverting input connected fromsquarer junction 78 o\ er a lead 235.

Inverter 46 has junctions 236 and 237. Inverter 46 also includes adifferential amplifier 238 ha\ing an inrerting input lead connected fromAND gate junction 228 and a non-inverting input lead connected fromjunction 236. A resistor 239 is connected from junction 236 to potential+\'1. A resistor 240 is connected from junction 236 to ground. Aresistor 24] is connected from junction 237 to potential +\'I. Amplifier238 has an output lead 242 connected tojunction 237. Junction 237 isconnected to the input of phase lock loop 47.

Phase locls loop 47 may or may not be entirely conventional. as desired.Phase lock loop 47 is shown in FIG. 6 including a phase detector 243. alow pass filter 244 and a \'CO 245. Phase detector 243 has input leads246 and 247. and an output lead 248. Low pass filter 244 has an inputlead 249. and an output lead 250. \'CO 245 has an input lead 251 and anoutput lead 252.

Phase detector input lead 246 is connected from the output lead ofinverter 46 at junction 237 shown in FIG. 5. In FIG. 6. the output lead248 of phase detector 243 is connected to the input lead 249 of low passfilter 244. The output lead 250 of low pass filter 244 is connected tothe input lead of \"CO 245 at 25L Both leads 252 and 247 are connectedto a common junction 253. Junction 253 is connected to the input ofdriver amplifier 248.

Low pass filter 2-H may be entirelv conventional. Alternativel low passfilter 2-H ma v be that shown in FIG. 7.

\'(O 245 is entirely comentional and ma v or mav not produce a sine waveoutput. as desired.

In FIG. 7. the input and output leads 2-89 and 250. respectively. of lowpass filter 2-H are again show it. Low pass filter 2-H has threejunctions 254. 255 and 256. resistor 257 is connected between lead 249and junction 254. A capacitor 258 is connected from junction 254 andground. A resistor 259 and a capacitor 260 are connected in series inthat order from junction 254 to junction 255. A resistor 261 isconnected from junction 256 to potential +\'I.

A resistor 262 is connected from junction 256 to ground. A differentialamplifier 263 is pro\ ided with an output lead 264 which is connected tojunction 255. The in\erting input of amplifier 263 is connected fromjunction 254. The Ittilt-IIH erting input of amplifier 263 is connectedfrom junction 256. Lead 250 is connected from junction 255.

Driver amplifier 48 of FIG. 2 is also shown in FIG. 8. In FIG. 8.\arious junctions are illustrated at 265. 266. 267. 268. 269. 270. 27I.272. 273. 274. 275. 276. 277. 273. I79. 280. ZXI. 282. 283 and 284.

Driver amplifier 48 has an input lead 285 connected from the output leadof phase lock loop 47 shown in FIG. 2. The output lead of phase lockloop 47 is illustrated at 286 in FIG. 6.

In FIG. 8. a capacitor 287 and a resistor 288 are connected in series inthat order from lead 285 to junction 265.

Svmbols at 289 and 290 indicate that a resistor 29l ma v be replacedbetween junction 266 and potential -\'I. A resistor 292 is connectedbetween junction 267 and potential-Y1. Junctions 265. 266 and 267 areconnected together. A differential amplifier 293 is pro- \ided with anoutput lead 294. Amplifier 293 has an in- \erting input lead connectedfrom junction 267. A resistor 295 is connected from the non-invertinginput lead of amplifier 293 to groundv A transistor 296 is proidedhaving a collector 297. an emitter 298 and a base 299. A resistor 300 isconnected from amplifier output lead 294 to base 299. Emitter 298 isconnected to junction 299. A resistor 30] is connected from junction 269to ground. A junction 302 is connected from junction 269. Junction 277is connected from junction 302.

Collector 297 is connected to junction 268. A train sistor is pro\idedat 303 having a collector 304. an emitter 305 and a base 306. Base 306is connected to junction 268. Emitter 305 is connected to junction 270.(ollector 304 is connected to junction 27]. Junctions 271 and 272 areconnected together. A resistor 307 is connected between junctions 268and 270. A capacitor 308 is connected between junctions 272 and 302. Aresistor 309 is connected from junction 272 to potential \'3. A resistor310 is connected between junctions 272 and 274. A transistor 311 isillustrated having a collector 312, an emitter 313 and a base 314. Base314 is connected from junction 27!. Collector 3I2 is con nected tojunction 273. Emitter 313 is connected to junction 274. Junctions 270.273. 275. 278 and 280 are all connected together.

transistor 319 is pnnided having a collector 320. an emitter 321 and abase 322. Base 322 is connected from junction 27-1. Collector 320 isconnected to junction 278. Emitter 32I is connected to junction 279. Acapacitor 323 and a resistor 324 are connected in series in that orderfrom junction 28] to junction 282. A resistor 325 is connected betweenjunctions 282 and 284. A resistor 326 is connected from junction 284 toground.

As shown in FIG. 8. drive coil 23 has leads 327 and 328 connected fromjunctions 281 and 284. respec tivel v.

A transistor 329 is provided in FIGv 8 including a collector 330. anemitter 33] and a base 332. A resistor 333 is connected from junction280 to base 332. A re sistor 334 is connected between junctions 280 and283. Emitter 331 is connected to junction 283. (ollector 330 isconnected to junction 268. Junction 282 is con nected to junction 265.

In FIG. 9. waveforms are illustrated at Fl to F8. The signal at F]appears at the output of preamplifier 26 shown in FIG. I and ma \ar fromit] to ltltltl mil|i- \olts. peak-to-peak.

The output signal of zero crossing detector 49 in FIG. 2 may be asillustrated at F2 in FIG. 9.

Waveform F3 and FIG. 9 ma v be the output signal of phase detector 50shown in FIG. 2.

The output signal of tracking filter 39 appearing on output lead 63thereofshown in FIG. 2 ma v be as illustrated at F4 in FIG. 9.

The output signal oftracking filter 38 on output lead 62 thereof shownin FIG. 2 ma v be illustrated at F5 in FIG. 9.

The output signal of phase detector 52 shown in FIG. 2 ma v he asillustrated at F6 in FIG. 9.

The output signal ofzero crossing detector 39 ma v be as indicated at F7in FIG. 9.

The output signal of one-shot 40 show u in FIG. 2 ma v he as indicatedat F8 in FIG. 9.

The output signal of sweep oscillator 57 shown in FIG. 2 ma valternatively be an v one of the waveforms G1. G2. and G3 shown in FIG.10. Sweep oscillators for the purpose of providing the waveforms G 1. G2and G3 are entirely conventional. Waneform GI is a triangular waveform.Waveform G2 is a saw-tooth wmeform.

The waveform G3 is fairly linear during periods TI and T2 and fairl vcurvilinear during periods T3 and T4. The waveform G3 is produced b anRC (resistancecapacitance) circuit.

The output lead 79 of saw-tooth generator 59 in FIG. 2 ma v have asignal thereon as illustrated in FIG. I]. The waveform of FIG. 12 isalternative to that shown in FIG. I I. Saw-tooth generator 59 andsquarer 44 maj be entirel v conventional. Alternatively. saw-toothgenerator 59 may produce the waveform of FIG. I2 in- \erted or not b aninverter to the waveform shown in FIG. 11.

In FIG. 5. amplifier 226 mav produce an output pulse as indicated at HIin FIG. 13 when the potential of junction 218 reaches the potential ofwiper 225 of po tentiometer 223 (assume FIG. II waveform I.

In FIG. I3. H2 is the output pulse on output lead 234 of amplifier 233.In FIG. 13. H3 is the output pulse which appears at junction 237 ininverter 46 shown in FIG. 5.

One embodiment of the digital function generator 30 is illustrated inFIG. 14. In Fl(i. 14. junctions are pro- \ided at 335. 336 and 337.

Herein. junction 335 may be described as a -terminal junction." Junction78 in FIG. 2. and other junctions therein. may be described as an outputjunction."

ln H0. 14. a di\ ide by-twenty di\ider 338. a di\ idcby-ten di\ ider 339and a di 'ide-by-tcn di\ider 340 are connected seriatim from an inputlead 341 of digital function generator 30 to junction 335. NAND gatesare pro ided at 342 and 343. The output of NAND gates 342 and 343 areimpressed upon a square law digital computer 344. A burst oscillator 345ha ing an output lead 346 connected to junction 336 provides one inputto each of the NAND gates 342 and 343 o\er leads 347 and 348. respcctiely. Each of the NAND gates 342 and 343 has tw o inputs. The other inputto NAND gate 343 is supplied o\ er a lead 349 connected from junction337. The other input to NAND gate 343 is connected oier a lead 350 fromjunction 335. An in 'erter 351 is connected from junction 335 tojunction 337. A difl'erentiator 352 is connected from junction 337 tosquare law digital computer 344. If desired. all of the differentiatorsdisclosed herein may or may not be identical to differentiator 353 shownin FIG. 18. Howe\er. other dil'ferentiators may also be employed.

An ol'fset digital computer 354 and a display unit 355 are connected insuccession in that order from square law digital computer 344. Off-setdigital computer 354 may be entirely comentional or as disclosed inapplication A8 or as disclosed herein Off-set digital computer 354receives serial groups of serial pulses. the number of pulses in eachgroup being directly proportional to the square of the period ofthesquare wa e appearing at terminal junction 335. This is likewisedirectly proportional to the square ofthe period of the square w a\cappearing on input lead 341 of digital function generator 30 shown inFl(i. 14.

The number of output pulses in a group impressed upon off-set digitalcomputer 354 may be described as being either equal to or directlyproportional to 41' where 'I' is the period into di\ider 338. Offsetdigital computer 354 then takes a group of these pulses and produces anoutput continually updated either equal to or directly proportional toIn the abo\e. .4 and If are constants.

Display unit 355 is entirely conventional. A different display unit maybe employed. if desired. Display unit 355 includes a logic circuit 356connected from off-set digital computer 354. and an indicator 357connected from the output of logic circuit 356. Indicator 357 can readin binary or decimal numbers directly the density of the fluid in which\ane 24 shown in H6. 1 is im mersed. Alternati ely. indicator 357 mayread in specific gra\ ity or otherwise.

Square law digital computer 344 is illustrated in FIG. 15. Square lawdigital computer 344 shown in FIG. 15 has a di\ ider 37' which is merelya counter that counts the output pulses front NAND gate 342.Dil'ferentiator 352 sets the count of di\ ider 37' to zero upon the leading edge of the pulse appearing at junction 337 and shown at E6 in FIG.21.

A rate multiplier 38' is connected from NAND gate 343 and produces onits output lead 358 a number of serial pulses in a group which is afraction of the total oil input pulses in a group such as a group shownat E8 in FIG. 2| dependent upon the number stored in the register of thecounter of di\ ider 37'. The output pulses in a group on output lead 358of rate multiplier 38' is then directly proportional to the square ofthe period of the square wa e either at junction 335 in H6. 14 or atinput lead 341 therein.

In Fl(i. 15. a switch matrix 33' is connected to a rate multiplier 359.Rate multiplier 359 is also connected front rate multiplier output lead358 to off-set digital computer 354. Rate multiplier 359. thus. has anoutput lead 360 which produces groups of pulses directly proportional toor equal to 4F. Switch matrix 33' has a set of manual operators 361 toproduce binary or decimal switch settings. Binary switches may beemployed. Al ternati ely. binary coded decimal IBCD) switches may beemployed. The factor A is set by setting the switch matris 33'. Thenumber of pulses in a group on the output lead 360 of rate multiplier359 is less than the input thereto. in part. depending upon the settingof the switch matris 33'.

hi FIG. 15. the counter of di\ ider 37' maybe entirely conventional. Asstated pre\iously. switch matri\ 33' may also be entirely con entional.The same is true of rate multipliers 38' and 359.

In accordance with one alternati e embodiment of the present in ention.di\ider 37. rate multiplier 38'. switch matrix 33' and rate multiplier359 may be as shown in FIG. 16. Divider 37' includes diyide-by-tendi\iders 362. 363. 364. 365 and 366. Rate multiplier 38" has ratemultiplier decades 367. 368. 369 and 370. respecti 'ely. connected fromBCD outputs of di\ideby-tcn di\iders 363. 364. 365 and 366. respecthely.

Note that di\ide-by-ten di\ider 366 carries the most significant decimaldigit. Rate multiplier decade 370. on the other hand. has the highestfrequency output. Thus. in order to produce the desired multiplicationof the decimal number contained in the registers 363-366. as a fraction.i.e.. less than unity. it is necessary to weigh di\ider 366 against thehighest frequency rate multiplier decade 37" and so forth.

Switch matrix 33' contains four BCD switches 371. 372. 373 and 374 haing adjustable knobs 375. 376. 377 and 378. respectively.

Rate multiplier 359 is identical to rate multiplier 38' and. therefore.will not be described further. From the foregoing. it will beappreciated that BCD switch 371 carries the most significant digit.

Typically. the square wave appearing at junction 335 in FlG. 14 has aperiod of 0.5 second. Typically. the pulse repetition frequency of theoutput signal of burst oscillator 345 in FIG. 14 is ltlt) kilohertz.Further. typically. the number of pulses in each of the groups at E8 andE9 in FIG. 21 are about 25.000.

Di ide-by-ten di\ ider 362 is employed in di\ider 37' to make sure thatthe number of pulses impressed upon rate multiplier 38' by NAND gate 343is about ten times the number stored in di\ide-by-ten di\iders 363-366.

Display unit 355 shown in FIG. 14 is entirely eonrentional. and for eachdecimal digit. it may appear as in FIG. 17. Display unit 355 is. thus.sold with logic circuit 358 to illuminate neon lamps 379 of theindicator 357. Such display units are sold by many companies. Forexample. one such display unit is sold by the Burroughs Corporationunder the trademark PLANAPLEX.

Rate multipliers 38' and 359 may be entirely comer tional. Any oneincluding. but not limited to. those sold by Motorola Semi-conductorProducts. Inc. and 'I'esas Instruments Incorporated may be employed. Thel\Iotorola model numbers are MC I4527AL and MC I4527CL. The TexasInstruments rate multipliers are described as synchronous ratemultipliers with circuit types SN7497 and SN4lo7. The foregoing Motorolaand Texas Instruments model numbers are generally given for what isdescribed herein as a rate multiplier decade which may be connectedseriatim ad infini tum. if desired.

As stated previously. off-set digital computers 354 shown in FIG. 15 maybe entirely conventional. One or many such computers may be employed.One such computer is sold as an MOS by Hughes Aircraft Company. This MOSis described further as a counter/latch- !decoder/driverHCTROl07D/HCTRO107F.

Alternatively. divider 37' and rate multiplier 38 of FIG. 15 may becombined in a changed form as shown in FIG. 18. Counters are provided at37" and 38". Counter 37" has a conventional logic circuit 380 and flipflops K1. K2. K3 KN forming a register 381. Dift'erentiator 352 isconnected to logic circuit 380. NAND gate 342 is connected to logiccircuit 380 through a divide-by-two divider 382.

Counter 38" has a logic circuit 383 and flip-flops L1. L2. L3 LNconnected therefrom to differentiators 353. 384. 385 386. respectively.

AND gates 387. 388. 389 390 are respectively connected fromdifferentiators 353. 384. 385 386.

and respectively from flip-flops K1. K2. K3 KN.

The output of each AND gate shown in FIG. 18 is connected to therespective input of an OR gate 391. the output of which is irnpreseedupon rate multiplier 359 shown in FIG. 15.

Note that flip-flop KN contains the most significant digit and theoutput frequency of flip-flop LN is the greatest. the output ofdifferentiator 386 being impressed in common with the l output ofHip-Hop KN on the two respective inputs of AND gate 390.

The outputs shown from all the flip-flops in register 381 from theflip-flops L1. L2. L3 LN in counter 38" are from the l outputs of thecorresponding flipflops.

The differentiators shown in FIG. 18 produce positive output pulses whenthe l output ofthe corresponding flip-flop goes high.

As stated previously. the flip-flops of register 381 in counter 37" areweighted in binary fashion according to the frequency of the outputpulses of the differentiators. None of the pulses at the outputs of theAND gates in FIG. 18 are coincident. This feature and the method ofoperation of all the structures shown in FIG. 18 is fully explained inapplication A9.

Counter 38" and logic circuit 383 receive an input from NAND gate 343shown in FIG. 14. and as shown in FIG. 18.

Ifdesired. the square law digital computer 344 shown in FIGS. 14 and 15may be further modified by changing rate multiplier 359 to that shown inFIG. 18. but by omitting counter 37" and substituting therefor a switchmatrix 392 as shown in FIG. 19.

An alternative embodiment ofdigital function gener ator 30 is indicatedat 30" in FIG. 20. Digital function generator 30" has an input lead 393.A divide-bytwenty divider 394. a divide-by-twenty-flve divider 395. adivide-by-two divider 396 and a divide-bytwo divider 397 are connectedin succession from input lead 393 to a terminal junction 398corresponding to terminal junction 335 in FIG. 14.

Digital function generator 30" has a burst oscillator 30' which may beidentical to burst oscillator 345 shown in FIG. 14. AND gates areprovided at 399 and 400 with their outputs connected respecthely at thepoints indicated in divider 37 and rate multiplier 38' of square lawdigital computer 10' shown in FIGS. 15 and 20. dividers 37' and 38'being the same in both the cases of FIGS. 14 and 20. For example. theoutput of gate 399 is connected to the input of rate multiplier 37' andthe output of AND gate 400 is connected to the input of rate multiplier38' shown in FIGS. 15 and 20.

In accordance with the foregoing. square law digital computer 10 in FIG.20 may be identical to square law digital computer 344 shown in FIG. 14.

AND gate 400 receives one input from junction 398 and another input fromoscillator 30'. AND gate 399 receives one input fron the output of burstoscillator 30'. and another input from the output of an imerter 401connected from junction 398. A lead 402 connects a junction 403 with ajunction 404. The output of in verter 401 is connected to junction 403.One input of AND gate 399 is connected from junction 403.

As before. a differentiator 405 is connected from junction 404 to thedivider 37' in square law digital computer 10' to reset the same. asbefore.

Digital function generator 30" shown in FIG. 20 has various otherjunctions 406. 407. 408. 409 and 410.

Differentiator 405 is connected to di\ider 37' of square law digitalcomputer 10' through a oneshot 411. The output ofone-shot 411 isconnected to a junc tion 412. Junction 412 is connected to square lawdigi tal computer 10. The output of AND gate 399 is con nected to squarelaw digital computer 10' through an AND gate 413 having a second inputfrom an inverter 414 connected from junction 412.

An inverter 415. a differentiator 416 and a one-shot 417 are connectedin succession in that order from junction 406 to junction 409. AND gates36' and 39' are provided. each of which receives an input from theoutput of one-shot 417 by a respective connection from junction 409.Junction 406 is connected from the output of divider 395 and to theinput ofdivider 396. Junc tion 407 is connected from the output ofdivider 396 and to the input of divider 397. Junctions 407 and 408 areconnected together. AND gate 30' has one input connected from junction408.

Junctions 404 and 410 are connected together. AND gates 36' and 39' bothreceive an input from the output of inverter 401 by respectiveconnections from junction 410. An inverter 418 is connected fromjunction 408 to another input of AND gate 36'.

Off-set digital computer 31' receives an input from square law digitalcomputer 10 and from the outputs of AND gates 36' and 39'.

An indicator 27' is connected from the output of offset digital computer31'. Off-set digital computer 31' may be decimal or binary. Theindicator 27' may be a simple indicator with one lamp for each binarystage or a decimal indicator as described hereinbefore and hereinafter.Indicator 27' may be entirely conventional. Off-set digital computer 31'may be conventional or of the type illustrated in FIG. 22 and disclosed.described and illustrated in application A8.

Oft set computer 31' in FIG. produces a hinary or a lunar coded decimaltBCDt otttput so that indicator 27 may he read directly. hinary ordecimal. in density or specific grtnity d. where d KIT 1- If and K [f/4f) where.

f is the pulse repetition frequency of hur t oscillator 2 ll) (althoughneed not he a multiple of Ill) where n is a positi\e integer largeenough to make A], less than unity. .-l is a constant less than unitydetermined hy the setting of su itch matri\ 33' in FIG. 15. B is apositi\e integer determined hy the setting of switch matriy 33' in FIG.15 or the switch matrix A shown in FIG. 2|. 1' is the period of square\\a\e E5 Ill FIG. 21.

K l li, l',,,l(

'1, is the maximum expected value of 7 over the operating range of theinstrument.

For]; Illll kilohertz and 00.1 second '1', l.ll

second. is. thus. 100.000 to make K,, I U5. Thus. K may he Iitltlt).This gi\es:

Either .4 or B may he positi e or negati e. The position of a switch 32'in FIG. 22 determines whether a counter count up 1.4 and H algehraicsigns the saute) or down 1.4 and I) algehraic signs different).

The pulses in each grouping at E8 go to rate multiplier 38' iii FIG. 15.Tlte pulses in each group E9 go to di ider 37' in FIG. 15. The output ofrate multiplier 38 is. therefore. equal to K.-l'I'-'.

The constants A and B may he determined empirically hy placing thedensitometer prohe 34' in two different lluids of two different knowndensities each time measuring T. The constants A and B may then hecalculated from two simultaneotts equations per patent pl.

Something ahout certain structures disclosed herein is discussed in thematerial immediately following. The importance of some of thisdiscussion may he apparent only from suhsequent explanations.

A main storage register D' is illustrated in FIG. 2|. As will hedescrihed. a predetermined numher B is entered in storage register Dperiodically.

A logic circuit is pro\ided at 13'. Logic circuit 13' has an input fromsquare law computer 10' through switch 32'.

In FIG. 2. the said predetermined numher B is peri odically entered instorage register D. as stated pre iously. The magnitude of thepredetermined number B may he selected or changed by operating hinary orhi nary coded decimal (BCD) switches. to he descrihed. which are locatedin a switch matrix A. The switches in matrix A are either connected froma positive potential \l or ground. The outputs of the switches aresampled and impressed upon storage register D periodically. A gatingpulse (E13 in FIG. 21) is impressed upon a gating circuit 8' for thispurpose.

fill

Gating circuit B is connected from matrix A to an OR gate matrix C. Theoutput of OR gate matrix C is then impressed upon storage register D.

Once the said predetermined numher B has heen entered into storageregister D. logic circuit 13' then controls the register D' to count upor down depending upon whether the signs ol A and B are the same or dilferent. s\\ itch 32' in FIG. 22 heing placed in the one or the othercorresponding positions thereof. respectiiely. on this account. Theouput of logic circuit [3' is. thus. impressed upon storage register Bthrough OR gate matriy I.ogic circuit 13' receives pulses to count fromswitch 32'. Logic circuit 13' recei es other inputs from storageregister D'.

From the foregoing. it will he appreciated that matrix with logiccircuit 13' and storage register D form either a count tip-count downcounter depending upon in which position switch 32 lies. This countermay he entirely con entional. if desired. The counter is indicated at23'.

The output of storage register D' is also sampled peri odically' hy agating circuit 24 which may he of the same type as gating circuit B.Gating circuit 24' receives pulses front AND gate 39 in FIG. 20 to causeit to sample the output of register D'. The output ofgating circuit 24is impressed upon a storage register 26'. The output of the storageregister 26' is impressed upon indicator 27.

If desired. indicator 27 may he a hinary indicator or a BCD indicator.

All ofthe structures D'.13'. A. B. C'. 24'. 26' and 27' may he entirelycontentional or may or may not he identical to the correspondingstructures disclosed iit application A8.

.-\lternati\'ely. indicator 27' may simply he a row of lamps eachconnected from the l output oteach of the flip-flops in storage register26.

Pulses are supplied from AND gate 36 to gating circuit B.

The purpose ofthe switch matrix A is to set. periodically. theflip-flops in storage register D to selected states.

Switch ntatrix A may ha e one double-pole. douhlethrow switch for eachhit or flip-flop in register D. Gating circuit B may ha e an AND gatefor the set l and set U inputs to each hit or flip-flop in register D'.The OR gate matrix C may have an OR gate for the set l and set U inputsof each hit in register D'.

The same outputs of the bits of register D are connected both to logiccircuit 13 and to gating circuit 24'.

The square ware at junction 406 in FIG. 20 is illustrated at E1 in FIG.22.

The square ware which appears at the output of inverter 415 in FIG. 20is illustrated at E2 in FIG. 22.

The square wave which appears at junction 407 in FIG. 20 is illustratedat E3 in FIG. 22.

The square wa e which appears at the output of in- \LTXLI' 418 in FIG.20 is illustrated at E4 in FIG. 22.

The square wave which appears at the terminal junc tion 398 in FIG. 20is illustrated at E5 in FIG. 22.

The square wave which appears at junction 403 in FIG. 20 is illustratedat E6 in FIG. 22.

The output of burst oscillator 30 is illustrated at E7 in FIG. 22.

The output of AND gate 400 in FIG. 20 is illustrated at E8 in FIG. 22.

The output of AND gate 399 in FIG. 20 is illustrated at E9 in FIG. 22.The output of differentiator 416 in FIG. 20 is illustrated at Ell) inFIG. 22.

The output of one-shot 417 shown in FIG. trated at [ill in FIG. 22.

The output of AND gate 39' shown in FIG. trated at EIZ in FIG. 22.

The output ofAND gate 36' shown in FI('|. trated at E13 in FIG. 22.

The phrase "utilization means. as used herein and in the claims. isherehy defined to include. hut not he limited to. an indicator. aprocess controller. or otherwise.

Although a symhol has heen used consistently in the drawings torepresent OR gates. it is to he understood that the symhol includes. hatis not limited to. a wire OR gate. Thus. one or tnore or all of thesymhols employed herein to represent an OR gate may or may not he a wireOR gate. as desired.

The phase OR gate." as used herein and in the claims. is herehy definedto include a NOR gate with or without an inverter. as may he necessaryor desirahle.

All of the said patents PI. P2. P3 and P4 are herehy incorporated hereinhy this reference hereto as though fully set forth herein here-at.

All of the said applications AI.A1.A3. A4. A5. Ah. A7. AH. A) and A are.hy this reference hereto. herehy incorporated herein as though fully setforth herein here-at.

As stated pre\iously. dri\er amplifier 48 shown in l-'l(iv 2 may heconventional or of a type disclosed in upplication A3.

In a sense. the amplifier of input circuit 36 shown in FIG. 2 alsooperates as a limiter.

.-\(i(' amplifier 37 shown in FIG. 2 also acts as an analog adder aswell as an .-\(i( amplifier.

In Fl(i. 1. digital function generator 30. having input lead 35. mayha\e the said input lead 35 connected from loop circuit output lead 33or from any other appropriate conductor in loop circuit 29. or fromjunction 77 as shown in Fl(i. 2.

Phase lock loops are conventional Most of phase lock loop 43 may heconventional. All of phase lock. loop 47 may he conventional. all oftheother structures illustrated in FIG. 2 heing conventional. However. notwill he taken that phase lock loop 43 receives a pulse input from outputlead 75 of clamp 42 when the said output lead 75 thereof is not groundedhy threshold detector 54. ()n the other hand. \(0 2|6 shown in FIG. 4and 245 shown in FIG. 6 may produce any comhinations of output signals.\IL. saw-tooth waves. sine waves and for square wa es. All of this isprior art. For ease of understanding. the outputs of \'(()s 216 and 245may he assumed to he sine waves.

In FIGS. 4 and 6. phase detectors 212 and 243. respectively. may he conentional phase detectors or four quadrant analog multipliers. Such phasedetectors easily produce a phase sensitive output signal. For example,see application A5.

Low pass filter 2-H shown in FIG. 7 may also he considered to he anintegrator. if desired.

All ofthe low pass filters disclosed herein mayor may not includeamplifiers. as desired. Amplifiers may he inserted anywhere in all ofthe circuitry disclosed herein.

20 is illus 20 is illus- Zll is illus- The phrase "AND gate." as usedherein and in the claims. is herehy defined to include an NAND gate withor without an inverter.

The phrase "NAND gate." as used herein and in the claims. is herehydefined to include an AND gate with or without an inverter.

Inder some circumstances. NAND gates 342 and 343 shown in FIG. [4 may heAND gates. if desired.

As indicated hereinhefore. hinary or hinary decimal systems maysometimes he used entirely in part. not at all. as shown or to a greateror less e\tent than that disclosed.

In FIG. 20. the input to AND gate 413 from inverter 4l-I suppresses theoutput of AND gate 4| during reset. In some cases. this circuitry may heomitted.

The phrase means to impress a signal." as used herein and in the claims.is herehy defined to include. hut not he limited to. a conductive leador otherwise.

The phrase means connecting." as used herein and in the claims. isherehy defined to include. hut not he limited to. a conductive lead. arate multiplier. an input circuit. an AGC amplifier. or other means. asuh combination. a circuit component. or otherwise.

The word continuous." as used herein and in the claims. is herebydefined to include. hut not he limited to. a register updatedperiodically.

The word "densitometer." as used herein and in the claims. is herehydefined to include. hut not he limited to. that shown with or without lutilization means. (I) a process controller. (3| a density or specificgrav ity indicator. or (-I) otherwise All the zero crossing detectorsdisclosed herein may he squarers. if desired.

The phrase specific granity." as used herein and in the claims. isherehy defined as the ratio of the density of a sample fluid to thedensity of a reference fluid. the reference fluid heing water or air orany other fluid.

All of the clamps disclosed herein may he omitted and gates used in lieuthereof.

What is claimed is:

I. A digital \ihration densitometer comprising; a prohe including ahousing. a vane. electrical means having an input lead. and a detectorhaving an output lead. said vane heing mounted on said housing. saidelectrical means heing mounted on said housing and heing responsive to afeedhacksignal impressed upon said input lead thereof to ihrate saidvane. said detector heing mounted on said housing in a position toreceive vihrations of said vane. said detector producing an outputsignal on said output lead thereof responsive to receipt of vihrationsfrom said vane. said output signal having an A.(. component of afrequency equal to the vihrational frequency of said vane; first meanshav' ing input and output leads. said first means input lead heingconnected from said detector output lead to prt duce a periodic signalon said first means output lead of a fundamental frequency equal to saidvihrational frequency; second means having input and output leads. saidsecond means input lead heing connected from said first means outputlead to said electrical means input lead to impress said feedback signalthereon. said feedback signal providing positive feedhack to cause saidprohe and said first and second means to act as a closed loopelectromechanical oscil lator. at least one of said first and secondmeans including an amplifier. at least one of said first and secondmeans heing constructed to provide gain for said loop to o\erconiedamping of said loop including damping of said \ane to an extent suchthat said electromechair ical oscillator oscillates continuously andsaid \ane ibrates continuously; at termainal junction. third meansha\ing input and output leads. said third means input and output leadsbeing connected from said first means output lead to said terminaijunction. re pectively. to impress a square ave on said terminaljunction hav ing a pulse repetition frequency IPRF! directlyproportional to said fundamental frequency and a mark-tospace ratio ofunity; first and second .\.-\.\D gates. each of said NAND gates havingfirst and second input leads and an output lead; a burst oscillatorliming a constant PRF large in comparison to that of said square \\a\e;an inverter having an input lead connected from said terminal junction.and an output lead connected to said second gate first input lead. saidfirst gate first lead being connected from said terminal junction. saidburst oscillator liming an output lead connected to the second lead ofeach ofsaid first and second gates; a di\ ider liming at least a firstinput lead. and a plurality of outputs leads. said divider acting as acounter and having a torage register with a constant count enteredtherein during alternate half periods of said square wave. pul escounted by said di\ ider being supplied oi er said first input leadthereof thereto. said di\ider first input lead being connected from oneof said gate output leads. a first rate multiplier having a plurality ofsetting input leads connected from respccti\e bits in said di \idcrregister. said first rate multiplier having a serial pulse input leadconnected from the other of said gate output lead and a serial pulseoutput lead: a manually adjustable switch inatri\ having a plurality ofoutput lead a second rate multiplier liming a plurality of setting inputleads connected respectively from said matri\ output leads. a serialpulse input lead connected from said first rate multiplier serial pulseoutput lead. and an output lead. said second rate multiplier produc inga number of serial pulses on the output lead thereof during saidalternate half periods of said square vvave directly proportional to .41where .4 is the constant introduced by adjustment of said switch matri\and 'I' is the period of said square \\d\|.. the number of pulsesproduced serially by said first rate multiplier on the said serial pulseoutput lead thereof being directly propor tional to T an off-set digitalcomputer having at least a first input lead connected from said secondrate multiplier serial pulse output lead. said computer liming aplurality of output leads and being adapted to produce digital outputsignals on said output leads thereof directly proportional to thequantity where b is a constant. said computer ha\ ing an adjustableswitch matrix. the adjustment of which varies B.

2. The invention as defined in claim 1. herein utilization means areconnected from said computer output leads 3. The imention as defined inclaim 2. wherein said computer output signals are binary coded decimalsig nals. said utili/ation means including a decimal indicator. theratio of I to the vibrational period ofsaid \ane being of a firstpredetermined magnitude. said burst os cillator PRF being of a secondpredetermined magni tude. said switch matrices being adjusted to causesaid indicator to read directly in eight per unit volume.

4. The invention as defined in claim 2. herein said computer outputsignals are binary coded decimal signals. said utilization meansincluding a decimal indicator. the ratio of 'I' to the ibrational periodof said \ane being of a first predetermined magnitude. said burstoscillator PRF being of a second predetermined magnitude. said switchmatrices being adjusted to cause said indicator to read directly inspecific gravity.

5. The iniention as defined in claim 1. including fourth means connectedfrom the first input lead of the one gate having the said one outputlead thereof to reset said divider to Zero on each leading edge of eachpulse of the square wave appearing on the first input lead of said onegate.

6. The invention as defined in claim 5. wherein said computer has secondand third input leads connected from said third means.

7. The invention as defined in claim 6. herein utili- .zation means areconnected from said computer output leads.

8. The invention as defined in claim 7. wherein said computer outputsignals are binary coded decimal slgnals. said utilization meansincluding a decimal indicator. the ratio of 'I' to the ibrational periodof said ane being of a first predetermined magnitude. said burst oscillator PRF being of a second predetermined magni tude. said switchmatrices being adjusted to cause said indicator to read directly inweight per unit volume.

9. The invention as defined in claim 7. wherein said computer outputsignals are binary coded decimal sig nals. said utilization meansincluding a decimai indicator. the ratio of 'l'to the \ibrational periodof said ane being of a first predetermined magnitude. said burstoscillator PRF being of a second predetermined magni' tude said switchmatrices being adjusted to cause said indicator to read directly inspecific gravity.

Hi. The in\ention as defined in claim 5. wherein utilization means areconnected from said computer output leads.

11. The invention as defined in claim 10. wherein said computer outputsignals are binary coded decimal signals. said utilization meansincluding a decimal indicator. the ratio of i" to the \ibrational periodof said vane being of a first predetermined magnitude. said burstoscillator PRF being of a second predetermined magnitude. said switchmatrices being adjusted to cause said indicator to read directly inweight per unit volume.

12. The invention as defined in claim 10. wherein said computer outputsignals are binary coded decimal signals. said utilization meansincluding a decimal indicator. the ratio of 'I' to the vibrationalperiod of said \ane being of a first predetermined magnitude. said burstoscillator PRF being of a second predetermined magnitude. said switchmatrices being adjusted to cause said indicator to read directly inspecific gravity.

IS. The invention as defined in claim 1. wherein said computer hassecond and third input leads connected from said third means.

14. The invention as defined in claim 13. wherein uti lization means areconnected from said computer output leads.

15. The invention as defined in claim l4. wherein said computer outputsignals are binary coded decimal signals. said utilization meansincluding a decimal indicator. the ratio of 'l to the vibrational periodof said \ane being of a first predetermined magnitude. said

1. A digital vibration densitometer comprising: a probe including ahousing, a vane, electrical means having an input lead, and a detectorhaving an output lead, said vane being mounted on said housing, saidelectrical means being mounted on said housing and being responsive to afeedback signal impressed upon said input lead thereof to vibrate saidvane, said detector being mounted on said housing in a position toreceive vibrations of said vane, said detector producing an outputsignal on said output lead thereof responsive to receipt of vibrationsfrom said vane, said output signal having an A.C. component of afrequency equal to the vibrational frequency of said vane; first meanshaving input and output leads, said first means input lead beingconnected from said detector output lead to produce a periodic signal onsaid first means output lead of a fundamental frequency equal to saidvibrational frequency; second means having input and output leads, saidsecond means input lead being connected from said first means outputlead to said electrical means input lead to impress said feedback signalthereon, said feedback signal providing positive feedback to cause saidprobe and said first and second means to act as a closed loopelectromechanical oscillator, at least one of said first and secondmeans including an amplifier, at least one of said first and secondmeans being constructed to provide gain for said loop to overcomedamping of said loop including damping of said vane to an extent suchthat said electromechanical oscillator oscillates continuously and saidvane vibrates continuously; a termainal junction; third means havinginput and output leads, said third means input and output leads beingconnected from said first means output lead to said terminal junction,respectively, to impress a square wave on said terminal junction havinga pulse repetition frequency (PRF) directly proportional to saidfundamental frequency and a markto-space ratio of unity; first andsecond NAND gates, each of said NAND gates having first and second inputleads and an output lead; a burst oscillator having a constant PRF largein comparison to that of said square wave; an inverter having an inputlead connected from said terminal junction, and an output lead connectedto said second gate first input lead, said first gate first lead beingconnected from said terminal junction, said burst oscillator having anoutput lead connected to the second lead of each of said first andsecond gates; a divider having at least a first input lead, and aplurality of outputs leads, said divider acting as a counter and havinga storage register with a constant count entered therein duringalternate half periods of said square wave, pulses counted by saiddivider being supplied over said first input lead thereof thereto, saiddivider first input lead being connected from one of said gate outpuTleads; a first rate multiplier having a plurality of setting input leadsconnected from respective bits in said divider register, said first ratemultiplier having a serial pulse input lead connected from the other ofsaid gate output leads and a serial pulse output lead; a manuallyadjustable switch matrix having a plurality of output leads; a secondrate multiplier having a plurality of setting input leads connectedrespectively from said matrix output leads, a serial pulse input leadconnected from said first rate multiplier serial pulse output lead, andan output lead, said second rate multiplier producing a number of serialpulses on the output lead thereof during said alternate half periods ofsaid square wave directly proportional to AT2 where A is the constantintroduced by adjustment of said switch matrix and T is the period ofsaid square wave, the number of pulses produced serially by said firstrate multiplier on the said serial pulse output lead thereof beingdirectly proportional to T2; an off-set digital computer having at leasta first input lead connected from said second rate multiplier serialpulse output lead, said computer having a plurality of output leads andbeing adapted to produce digital output signals on said output leadsthereof directly proportional to the quantity AT2 + B where B is aconstant, said computer having an adjustable switch matrix, theadjustment of which varies B.
 2. The invention as defined in claim 1,wherein utilization means are connected from said computer output leads.3. The invention as defined in claim 2, wherein said computer outputsignals are binary coded decimal signals, said utilization meansincluding a decimal indicator, the ratio of T to the vibrational periodof said vane being of a first predetermined magnitude, said burstoscillator PRF being of a second predetermined magnitude, said switchmatrices being adjusted to cause said indicator to read directly inweight per unit volume.
 4. The invention as defined in claim 2, whereinsaid computer output signals are binary coded decimal signals, saidutilization means including a decimal indicator, the ratio of T to thevibrational period of said vane being of a first predeterminedmagnitude, said burst oscillator PRF being of a second predeterminedmagnitude, said switch matrices being adjusted to cause said indicatorto read directly in specific gravity.
 5. The invention as defined inclaim 1, including fourth means connected from the first input lead ofthe one gate having the said one output lead thereof to reset saiddivider to zero on each leading edge of each pulse of the square waveappearing on the first input lead of said one gate.
 6. The invention asdefined in claim 5, wherein said computer has second and third inputleads connected from said third means.
 7. The invention as defined inclaim 6, wherein utilization means are connected from said computeroutput leads.
 8. The invention as defined in claim 7, wherein saidcomputer output signals are binary coded decimal signals, saidutilization means including a decimal indicator, the ratio of T to thevibrational period of said vane being of a first predeterminedmagnitude, said burst oscillator PRF being of a second predeterminedmagnitude, said switch matrices being adjusted to cause said indicatorto read directly in weight per unit volume.
 9. The invention as definedin claim 7, wherein said computer output signals are binary codeddecimal signals, said utilization means including a decimal indicator,the ratio of T to the vibrational period of said vane being of a firstpredetermined magnitude, said burst oscillator PRF being of a secondpredetermined magnitude, said switch matrices being adjusted to causesaid indicator to read directly in specific gravity.
 10. The inventionas defined in claim 5, wherein utilization means are connected from saidcomputer ouTput leads.
 11. The invention as defined in claim 10, whereinsaid computer output signals are binary coded decimal signals, saidutilization means including a decimal indicator, the ratio of T to thevibrational period of said vane being of a first predeterminedmagnitude, said burst oscillator PRF being of a second predeterminedmagnitude, said switch matrices being adjusted to cause said indicatorto read directly in weight per unit volume.
 12. The invention as definedin claim 10, wherein said computer output signals are binary codeddecimal signals, said utilization means including a decimal indicator,the ratio of T to the vibrational period of said vane being of a firstpredetermined magnitude, said burst oscillator PRF being of a secondpredetermined magnitude, said switch matrices being adjusted to causesaid indicator to read directly in specific gravity.
 13. The inventionas defined in claim 1, wherein said computer has second and third inputleads connected from said third means.
 14. The invention as defined inclaim 13, wherein utilization means are connected from said computeroutput leads.
 15. The invention as defined in claim 14, wherein saidcomputer output signals are binary coded decimal signals, saidutilization means including a decimal indicator, the ratio of T to thevibrational period of said vane being of a first predeterminedmagnitude, said burst oscillator PRF being of a second predeterminedmagnitude, said switch matrices being adjusted to cause said indicatorto read directly in weight per unit volume.
 16. The invention as definedin claim 14, wherein said computer output signals are binary codeddecimal signals, said utilization means including a decimal indicator,the ratio of T to the vibrational period of said vane being of a firstpredetermined magnitude, said burst oscillator PRF being of a secondpredetermined magnitude, said switch matrices being adjusted to causesaid indicator to read directly in specific gravity.
 17. A vibrationaldensitometer comprising: an electromechanical oscillator including aprobe and a loop circuit, said probe and said loop circuit each havingan input lead and an output lead, said probe output lead being connectedto said loop circuit input lead, said loop circuit output lead beingconnected to said probe input lead, said probe having a vibratablestructure, said loop circuit having an output junction and first meansto cause a periodic signal to appear at said output junction of afundamental frequency equal to the frequency at which said structurevibrates; a terminal junction; second means connected between saidjunctions for impressing a square wave on said terminal junction havinga period directly proportional to that of said periodic signalfundamental frequency and having a mark-to-space ratio equal to unity;first and second NAND gates, each of said NAND gates having first andsecond input leads and an output lead; a burst oscillator having aconstant pulse repetition frequency large in comparison to that of saidsquare wave; an inverter having an input lead connected from saidterminal junction, and an output lead connected to said second gatefirst input lead, said first gate first input lead being connected fromsaid terminal junction, said burst oscillator having an output leadconnected to the second lead of each of said first and second gates; adivider having at least a first input lead, said divider acting as acounter and having a storage register with a constant count enteredtherein during alternate half periods of said square wave, said storageregister having a plurality of output leads, pulses counted by saiddivider being supplied over said first input lead thereof, said dividerfirst input lead being connected from one of said gate output leads; arate multiplier having a plurality of setting input leads connected fromrespective divider register output leads, said rate multiplier having aserial pulse inpUt lead connected from the other of said gate outputleads and a serial pulse output lead, said rate multiplier producingserial groups of serial pulses on said output lead thereof, the numberof pulses in a rate multiplier group being directly proportional to T2where T is the period of said square wave; an off-set digital computerhaving an input lead and a plurality of output leads; and third meanshaving an input lead connected from said rate multiplier serial pulseoutput lead, and an output lead connected to said off-set computer inputlead, said third means producing serial groups of serial pulses, thenumber of pulses in a third means group being directly proportional toAT2, where A is a constant, said off-set computer producing signals onsaid output leads thereof representative of a digital number of directlyproportional to AT2 + B where B is a constant.
 18. The invention asdefined in claim 17, wherein said third means includes fourth means toadjust manually the magnitude of A, said off-set computer includingfifth means to adjust manually the magnitude of B.
 19. The invention asdefined in claim 18, wherein utilization means are connected from saidoff-set computer output leads.
 20. The invention as defined in claim 19,wherein said off-set computer output signals are binary coded decimalsignals, said utilization means including a decimal indicator, the ratioof T to the vibrational period of said vane being of a firstpredetermined magnitude, said burst oscillator pulse repetitionfrequency being of a second predetermined magnitude, said fourth meansand said fifth means adjusting A and B, respectively, to cause saidindicator to read directly in weight per unit volume.
 21. The inventionas defined in claim 19, wherein said off-set computer output signals arebinary coded decimal signals, said utilization means including a decimalindicator, the ratio of T to the vibrational period of said vane beingof a first predetermined magnitude, said burst oscillator pulserepetition frequency being of a second predetermined magnitude, saidfourth means and said fifth means adjusting A and B, respectively, tocause said indicator to read directly in specific gravity.
 22. Theinvention as defined in claim 18, including sixth means connected fromthe first input lead of the one gate having the said one output leadthereof to reset said divider to zero on each leading edge of said pulseof the square wave appearing on the first input lead of said one gate.23. The invention as defined in claim 22, wherein said off-set computerhas second and third input leads connected from said second means. 24.The invention as defined in claim 23, wherein utilization means areconnected from said off-set computer output leads.
 25. The invention asdefined in claim 24, wherein said off-set computer output signals arebinary coded decimal signals, said utilization means including a decimalindicator, the ratio of T to the vibrational period of said vane beingof a first predetermined magnitude, said burst oscillator pulserepetition frequency being of a second predetermined magnitude, saidfourth means and said fifth means adjusting A and B, respectively, tocause said indicator to read directly in weight per unit volume.
 26. Theinvention as defined in claim 24, wherein said off-set computer outputsignals are binary coded decimal signals, said utilization meansincluding a decimal indicator, the ratio of T to the vibrational periodof said vane being of a first predetermined magnitude, said burstoscillator pulse repetition frequency being of a second predeterminedmagnitude, said fourth means and said fifth means adjusting A and B,respectively, to cause said indicator to read directly in specificgravity.
 27. The invention as defined in Claim 22, wherein utilizationmeans are conNected from said off-set computer output leads.
 28. Theinvention as defined in claim 27, wherein said off-set computer outputsignals are binary coded decimal signals, said utilization meansincluding a decimal indicator, the ratio of T to the vibrational periodof said vane being of a first predetermined magnitude, said burstoscillator pulse repetition frequency being of a second predeterminedmagnitude, said fourth means and said fifth means adjusting A and B,respectively, to cause said indicator to read directly in weight perunit volume.
 29. The invention as defined in claim 27, wherein saidoff-set computer output signals are binary coded decimal signals, saisutilization means including a decimal indicator, the ratio of T to thevibrational period of said vane being of a first predeterminedmagnitude, said burst oscillator pulse repetition frequency being of asecond predetermined magnitude, said fourth means and said fifth meansadjusting A and B, respectively, to cause said indicator to readdirectly in specific gravity.
 30. The invention as defined in claim 18,wherein said computer has second and third input leads connected fromsecond means.
 31. The invention as defined in claim 30, whereinutilization means are connected from said offset computer output leads.32. The invention as defined in claim 31, wherein said off-set computeroutput signals are binary coded decimal signals, said utilization meansincluding a decimal indicator, the ratio of T to the vibrational periodof said vane being of a first predetermined magnitude, said burstoscillator pulse repetition frequency being of a second predeterminedmagnitude, said fourth means and said fifth means adjusting A and B,respectively, to cause said indicator to read directly in weight perunit volume.
 33. The invention as defined in claim 31, wherein saidoff-set computer output signals are binary coded decimal signals, saidutilization means including a decimal indicator, the ratio of T to thevibrational period of said vane being of a first predeterminedmagnitude, said burst oscillator pulse repetition frequency being of asecond predetermined magnitude, said fourth means and said fifth meansadjusting A and B, respectively, to cause said indicator to readdirectly in specific gravity.
 34. A vibration densitometer comprising:an electromechanical oscillator including a probe and a loop circuit,said probe and said loop circuit each having an input lead and an outputlead, said probe output lead being connected to said loop circuit inputlead, said loop circuit output lead being connected to said probe inputlead, said probe having a vibratable structure, said loop circuitincluding a tracking filter having first and second input leads andfirst and second output leads, said tracking filter being constructed toproduce first and second output signals on said first and second outputleads thereof, respectively, said first tracking filter output signallagging said second tracking filter output signal in phase by 90*; firstmeans connecting said loop circuit input lead to said tracking filterfirst input lead; second means having input and output leads connectedrespectively from and to said tracking filter second output lead andsaid tracking filter second input lead, said first means impressing asignal on said tracking filter first input lead of a frequency equal tothe frequency Delta t which said structure vibrates, said second meansapplying a control signal to said tracking filter second input lead of atype to cause the tracking filter passband to move to a locationstraddling the frequency of the signal impressed upon said trackingfilter first input lead; a zero crossing detector having input andoutput leads; a phase detector having input and output leads; a low passfilter having input and output leads, said zero crossing detector havingsaid output and input leads thereoF connected respectively to saidtracking filter first output lead and said phase detector input lead,said phase detector output lead being connected to said low pass filterinput lead; an output junction; third means having an input leadconnected from said low pass filter output lead, and an output leadconnected to said output junction, said third means impressing a signalon said output junction of said vibrational frequency; fourth meanshaving input and output leads connected to said output junction and tosaid loop circuit output lead, respectively, said fourth means excitingsaid probe in a manner to cause said structure to vibrate; fifth meanshaving an input lead connected from said output junction, said fifthmeans having output lead means and being constructed to produce outputsignals on said output lead thereof directly proportional to AT2 + Bwhere T is the reciprocal of said vibrational frequency, and A and B areconstants; and utilization means having input lead means connected fromsaid fifth means output lead means.
 35. The invention as defined inclaim 34, wherein said utilization means is an indicator for themagnitude of the signal impressed thereon and calibrated in density. 36.The invention as defined in claim 34, wherein said utilization means isan indicator for the magnitude of the signal impressed thereon andcalibrated in specific gravity.
 37. The invention as defined in claim34, wherein said first means has a series connected stage including anautomatic gain control (AGC) amplifier having an AGC input leadconnected from said zero crossing detector output lead.
 38. Theinvention as defined in claim 37, wherein said utilization means is anindicator for the magnitude of the signal impressed thereon andcalibrated in density.
 39. The invention as defined in claim 37, whereinsaid utilization means is an indicator for the magnitude of the signalimpressed thereon and calibrated in specific gravity.
 40. A vibrationdensitometer comprising: an electromechanical oscillator including aprobe and a loop circuit, said probe and said loop circuit each havingan input lead and an output lead, said probe output lead being connectedto said loop circuit input lead, said loop circuit output lead beingconnected to said probe input lead, said probe having a vibratablestructure, said loop circuit including a first clamp having first andsecond input leads and an output lead; first means connected betweensaid loop circuit input lead and said first clamp first input lead toimpress a periodic signal on said first clamp first input lead of afundamental frequency equal to the frequency of vibration of saidstructure; a sweep oscillator having power input and output leads; athreshold detector having input and output leads, said thresholddetector producing a step signal on its output lead when the inputsignal magnitude on its input lead passes through a predeterminedmagnitude; second means having input and output leads connected to saidfirst means and said threshold detector input lead, respectively, tosupply a signal to said threshold detector on said input lead thereof ofa magnitude proportional to the magnitude of the signal passing throughsaid probe producing an output signal on its output lead of a frequencyequal to said frequency of vibration; an inverter having input andoutput leads, said threshold detector having its output lead connectedto said first clamp second input lead and to said inverter input lead; aphase lock loop including a phase detector having first and second inputleads and an output lead, said first clamp output lead being connectedto said phase detector first input lead, said inverter output lead beingconnected to said sweep oscillator power input lead; said phase lockloop having a voltage controlled oscillator with an input lead connectedfrom an output lead of said phase detector and an output lead connectedto said phase detector second input lead; thirD means connecting theoutput of said sweep oscillator to the input of said voltage controlledoscillator; fourth means connected from said voltage controlledoscillator output lead to said loop circuit output lead to impress asignal on said probe input lead to cause said structure to be vibrated;and utilization means connected from said fourth means.
 41. Theinvention as defined in claim 40, including a second clamp having firstand second input leads and an output lead, said second clamp first inputlead being connected from said inverter output lead, an output junction,said fourth means including means connected from said voltage controlledoscillator output lead to said output junction to impress a square waveon said output junction having a fundamental frequency equal to saidvibrational frequency, said second clamp second input lead beingconnected from said output junction, said first means including anautomatic gain control (AGC) amplifier having an AGC input lead, saidsecond clamp output lead being connected to said gain control inputlead.